Category:Verilog

From Rosetta Code
Language
Verilog
This programming language may be used to instruct a computer to perform a task.
See Also:


Listed below are all of the tasks on Rosetta Code which have been solved using Verilog.
Your Help Needed
If you know Verilog, please write code for some of the tasks not implemented in Verilog.
This page uses content from Wikipedia. The original article was at Verilog. The list of authors can be seen in the page history. As with Rosetta Code, the text of Wikipedia is available under the GNU FDL. (See links for details on variance)

In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL, is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits.


This page is a stub. It needs more information! You can help Rosetta Code by filling it in!

Subcategories

This category has the following 3 subcategories, out of 3 total.

Pages in category "Verilog"

The following 3 pages are in this category, out of 3 total.