Page history
11 March 2024
24 October 2023
imported>Bmoore9999
no edit summary
+114
imported>Bmoore9999
Created page with "=={{header|VHDL}}== ===Encoder=== <syntaxhighlight lang="vhdl"> entity nrzi_encoder is port( clk :in std_logic; d :in std_logic; q :out std_logic ); end entity; architecture rtl of nrzi_encoder is begin process(clk) begin if (d = '1') then if (qint = '0') then qint <= '1'; else qint <= '0'; end if; end if; end process; q <= qint; end architecture;..."
+1,013