NRZM
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NRZ(M) | NRZM | Non-return-to-zero mark | Serializer mapping {0: constant, 1: toggle}. |
FreeBASIC
FreeBASIC does not have native support for some of the features used in the VHDL examples, so these codes are a simplification.
In both cases, data() is the input array that contains the data to be encoded or decoded, and signal() is the output array that will contain the encoded signal or the decoded data. Both arrays must have the same length. The encoded signal and data are represented as arrays of integers, where '0' represents a low level and '1' represents a high level.
Encoder
Sub NRZI_Encoder (dato() As Integer, signal() As Integer)
Dim As Integer i, level = 0
For i = Lbound(dato) To Ubound(dato)
If dato(i) = 1 Then level = Not level
signal(i) = level
Next i
End Sub
Decoder
Sub NRZI_Decoder (signal() As Integer, dato() As Integer)
Dim As Integer i, lastLevel = signal(Lbound(signal))
For i = Lbound(signal) + 1 To Ubound(signal)
If signal(i) = lastLevel Then
dato(i - 1) = 0
Else
dato(i - 1) = 1
lastLevel = signal(i)
End If
Next i
End Sub
VHDL
Encoder
entity nrzi_encoder is
port(
clk :in std_logic;
d :in std_logic;
q :out std_logic
);
end entity;
architecture rtl of nrzi_encoder is
begin
process(clk)
begin
if (d = '1') then
if (qint = '0') then
qint <= '1';
else
qint <= '0';
end if;
end if;
end process;
q <= qint;
end architecture;
Decoder
entity nrzi_decoder is
port(
clk :in std_logic;
d :in std_logic;
q :out std_logic
);
end entity;
architecture rtl of nrzi_decoder is
signal lastd :std_logic := '0';
begin
process(clk)
begin
if (rising_edge(clk)) then
if (d = lastd) then
q <= '0';
else
q <= '1';
end if;
lastd <= d;
end if;
end process;
end architecture;