NRZS

NRZ(S)

NRZS

Non-return-to-zero space

Serializer mapping {0: toggle, 1: constant}.

FreeBASIC

FreeBASIC does not have native support for some of the features used in the VHDL examples, so these codes are a simplification.

In both cases, data() is the input array that contains the data to be encoded or decoded, and signal() is the output array that will contain the encoded signal or the decoded data. Both arrays must have the same length. The encoded signal and data are represented as arrays of integers, where '0' represents a low level and '1' represents a high level.

Encoder

Sub NRZS_Encoder (dato() As Integer, signal() As Integer)
    Dim As Integer i, level = 0
    For i = Lbound(dato) To Ubound(dato)
        If dato(i) = 0 Then level = Not level
        signal(i) = level
    Next i
End Sub

Decoder

Sub NRZS_Decoder (signal() As Integer, dato() As Integer)
    Dim As Integer i, lastLevel = signal(Lbound(signal))
    For i = Lbound(signal) + 1 To Ubound(signal)
        If signal(i) = lastLevel Then
            dato(i - 1) = 1
        Else
            dato(i - 1) = 0
            lastLevel = signal(i)
        End If
    Next i
End Sub

VHDL

Encoder

library ieee;
use ieee.std_logic_1164.all;

entity nrzs_encoder is
port(
    clk :in  std_logic;
    d   :in  std_logic;
    q   :out std_logic
);
end entity;

architecture rtl of nrzs_encoder is

    function nrzi_s(
        signal curr :in std_logic;
        signal prev :in std_logic
    ) return std_logic is

        if (curr = '0') then
            return not prev;
        else 
            return prev;
        end if;
    end function;

begin

    process(clk)   
    begin
        q <= nrzi_s(d, q);
    end process;

end architecture;

Decoder

entity nrzi_decoder is
port(
    clk :in  std_logic;
    d   :in  std_logic;
    q   :out std_logic
);
end entity;

architecture rtl of nrzi_decoder is
    signal lastd :std_logic := '0';
begin

    process(clk)
    begin
        if (rising_edge(clk)) then
            if (d = lastd) then
                q <= '0';
            else 
                q <= '1';
            end if;
            lastd <= d;
        end if;
    end process;

end architecture;