Zero to the zero power: Difference between revisions
Zero to the zero power en Verilog
(Zero to the zero power en Openscad) |
(Zero to the zero power en Verilog) |
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{{Out}}
<pre>1</pre>
=={{header|Verilog}}==
<lang Verilog>module main;
initial begin
$display("0 ^ 0 = ", 0**0);
$finish ;
end
endmodule</lang>
{{out}}
<pre>0 ^ 0 = 1</pre>
=={{header|Visual Basic .NET}}==
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