Anonymous user
Four bit adder: Difference between revisions
→{{header|MyHDL}}
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=={{header|MyHDL}}==
{{Verbose Code}}
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<lang MyHDL>PRINT "#!/usr/bin/env python
# -*- coding: utf8 -*-
from myhdl import always_comb, ConcatSignal, delay, intbv, Signal, \
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# declare I/
N=4
a = Signal(intbv(0)[N:])
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sim = Simulation(tb())
sim.run()
"</lang>
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