Seven-sided dice from five-sided dice: Difference between revisions

m
→‎{{header|Verilog}}: Fixed typo (teh → the)
m (→‎{{header|Verilog}}: Fixed typo (teh → the))
Line 1,905:
/// seven_sided_dice : ///
/// Synthsizeable module that using a 5 sided dice as a black box ///
/// is able to reproduce tehthe outcomes if a 7-sided dice ///
///////////////////////////////////////////////////////////////////////////////
module seven_sided_dice(
Anonymous user