NRZM: Difference between revisions
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imported>Bmoore9999 (Created page with "=={{header|VHDL}}== ===Encoder=== <syntaxhighlight lang="vhdl"> entity nrzi_encoder is port( clk :in std_logic; d :in std_logic; q :out std_logic ); end entity; architecture rtl of nrzi_encoder is begin process(clk) begin if (d = '1') then if (qint = '0') then qint <= '1'; else qint <= '0'; end if; end if; end process; q <= qint; end architecture;...") |
imported>Bmoore9999 No edit summary |
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=={{header|VHDL}}== |
=={{header|VHDL}}== |
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{| class="wikitable" |
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|'''NRZ(M)''' |
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|NRZM |
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|Non-return-to-zero mark |
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|Serializer mapping {0: constant, 1: toggle}. |
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|} |
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===Encoder=== |
===Encoder=== |
Revision as of 15:52, 24 October 2023
VHDL
NRZ(M) | NRZM | Non-return-to-zero mark | Serializer mapping {0: constant, 1: toggle}. |
Encoder
entity nrzi_encoder is
port(
clk :in std_logic;
d :in std_logic;
q :out std_logic
);
end entity;
architecture rtl of nrzi_encoder is
begin
process(clk)
begin
if (d = '1') then
if (qint = '0') then
qint <= '1';
else
qint <= '0';
end if;
end if;
end process;
q <= qint;
end architecture;
Decoder
entity nrzi_decoder is
port(
clk :in std_logic;
d :in std_logic;
q :out std_logic
);
end entity;
architecture rtl of nrzi_decoder is
signal lastd :std_logic := '0';
begin
process(clk)
begin
if (rising_edge(clk)) then
if (d = lastd) then
q <= '0';
else
q <= '1';
end if;
lastd <= d;
end if;
end process;
end architecture;