Gray code: Difference between revisions

Content added Content deleted
Line 4,781: Line 4,781:
output wire [SIZE-1:0] o_count_binn
output wire [SIZE-1:0] o_count_binn
);
);

`define CQ #1


reg [SIZE-1:0] state_gray;
reg [SIZE-1:0] state_gray;
Line 4,791: Line 4,789:
always @(posedge i_clk or negedge i_rst_n) begin
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) begin
if (!i_rst_n) begin
state_gray <= `CQ 0;
state_gray <= 0;
state_binn <= `CQ 0;
state_binn <= 0;
end
end
else begin
else begin
state_gray <= `CQ logic_gray;
state_gray <= logic_gray;
state_binn <= `CQ logic_binn;
state_binn <= logic_binn;
end
end
end
end
Line 4,807: Line 4,805:
assign o_count_gray = state_gray;
assign o_count_gray = state_gray;
assign o_count_binn = state_binn;
assign o_count_binn = state_binn;

`undef CQ


endmodule
endmodule