Information for "Category:Verilog"
Basic information
| Display title | Category:Verilog |
| Default sort key | Verilog |
| Page length (in bytes) | 451 |
| Namespace ID | 14 |
| Namespace | Category |
| Page ID | 3212 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
Category information
| Total number of members | 51 |
| Number of pages | 48 |
| Number of subcategories | 3 |
| Number of files | 0 |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | MikeMol (talk | contribs) |
| Date of page creation | 06:25, 4 February 2010 |
| Latest editor | rosettacode>Parsleyfirefly |
| Date of latest edit | 21:17, 3 December 2010 |
| Total number of edits | 2 |
| Recent number of edits (within past 180 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (9) | Templates used on this page: |