Talk:Four bit adder: Difference between revisions

m
Line 39:
 
These images (except Xor) are not ready
{|
<!-- {| -->
|-
! NOT !! AND !! OR !! XOR
|-
| [[Image:Not.svg|thumb|64px|alt=NOT gate]]
| [[Image:And.svg|thumb|64px|alt=AND gate]]
| [[Image:Or.svg|thumb|64px|alt=OR gate]]
| [[Image:Xor.svg|thumb|64px|alt=XOR gate]]
<!-- |} -->
 
We imagine that these are "binary" gates, accepting two inputs and yielding one output, save for '''NOT''' which is an unary gate: it has an input and an output. At each input and output corresponds a [[wp:Lead (electronics)|pin]]. Commonly gates are [[wp:Integrated circuit packaging|packaged]] together into a single [[wp:Chip carrier|package]], containing e.g. [[wp:7400 series|four gates]], and they exist also [[wp:Integrated circuit|chips]] that "implement" a N-input '''OR''', '''AND'''... However these can be done using several gates in their binary "version", so we don't consider them ''elemental''. Indeed considering the [[wp:De Morgan's laws|De Morgan laws]] and other amenities from boolean algebra, we can see that our set of gates is still not really the minimal elemental set of gates. Indeed the discussion about which gates can be considered elemental should not ignore how these gates are created in hardware using "transistors", and the fact that a single purposely chosen gate is all we need to create our circuits. For example, the '''NAND''' gates is a gate similar to the '''AND''', but the output is inverted (''not''ed). All the other gates can be realized using this single gate! So that the minimal set of elemental gates can contain just one element, e.g. the '''NAND''', but the '''NOR''' can be used similarly (see for example [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/nand.html|this link], that shows how a CMOS '''NAND''' and '''AND''' are realized and how they work; observe that the '''NAND''' has 4 transistors while the '''AND''' needs six transistors).