Anonymous user
Talk:Four bit adder: Difference between revisions
→Motivations behind the task (and point 1 (RC domain))
(→Extra long, educational version of the task (draft): Something for the encyclopaedia category?) |
|||
Line 153:
: It sounds like something on the scale of RCRPG/RCBF/RCSNUSP, and it has its own kinds of interest. I'd say go ahead and try it, but don't use [[Template:Task]] for it, at least not soon. I'd suggest you first try modeling the basic gates (including allowing XOR to be done natively), then extend to half adder, full adder, flip-flops, etc. I noticed you didn't account for the possibility of clocks and/or propagation. (I thought of doing a C++ example that had a Clock() method, for example.)
: Find a corner of the wiki and see what you come up with; there are obviously already some HW-savvy folks around here, and maybe you'll come up with something that can be incorporated/adapted/fit with the wiki in general. Also, let me know if you come up with a gate-logic implementation of BF. My step-dad was interested in doing that a while back. ;) --[[User:Short Circuit|Michael Mol]] 18:57, 16 June 2010 (UTC)
The idea as whole is enough large to be in the project category. Constructive blocks however are simple task of their own (task used in the general way, not as "RC task"); having a library of these blocks should then make it simpler (!) to realized the final project.
Indeed, as the "4-bit adder" task was done, it proved to be badly planned. The general way I set up things do not allow for all the needed things to do all kinds of circuits needed for the final project. E.g. as I did both C and Sather impl can't describe a latch at all, even expanding to allow a clock; deeper thoughts made me believe Go too could have problem, putting the program in a never-ending wait for ready signal, but I didn' analyse it further.
As already said, my aim is not to build things too much hardware-design bound. But I am realizing that maybe some "real" simulation trick must be used sooner or later (again, latch ... I'll be going to experiment on my own before saying more, but I vaguely see they can be problematic in a straightforward approach). Being curious to answer the question "is this idea not new?", I searched the net and '''of course''' I've found already done stuffs, but as real hardware design (e.g. the harp project, and YASEP), very interesting for anybody interested in.
I think the "processor" can have as instruction set BF, with the understanding that <tt>.</tt> and <tt>,</tt> can interface the cpu to any suitable device (that must be projected purposely) and likely more instructions for jump could be useful to augment performance (the <nowiki>[</nowiki> needs look-ahead and a <nowiki>[</nowiki>-stack ...). Currently my ideas about how all this can be realized are rather foggy; however I've installed some VHDL tools, going to see how this task would look with it. -[[User:ShinTakezou|ShinTakezou]] 10:36, 17 June 2010 (UTC)
| |||