Anonymous user
Talk:Four bit adder: Difference between revisions
m
→Extra long, educational version of the task (draft): syntax and typofix
(→Extra long, educational version of the task (draft): new section) |
m (→Extra long, educational version of the task (draft): syntax and typofix) |
||
Line 28:
== Extra long, educational version of the task (draft) ==
I was thinking about making the task description better. This draft likely is too long to be suitable; maybe also too much educational, even though still "incomplete" someway. I don't dislike it totally however. Suggestions? --[[User:ShinTakezou|ShinTakezou]] 17:21, 16 June 2010 (UTC)
'''Preface'''
Line 39:
These images (except Xor) are not ready
<!-- {| -->
|-
! NOT !! AND !! OR !! XOR
Line 47:
| [[Image:Or.svg|thumb|64px|alt=OR gate]]
| [[Image:Xor.svg|thumb|64px|alt=XOR gate]]
<!-- |} -->
We imagine that these are "binary" gates, accepting two inputs and yielding one output, save for '''NOT''' which is an unary gate: it has an input and an output. At each input and output corresponds a [[wp:Lead (electronics)|pin]]. Commonly gates are [[wp:Integrated circuit packaging|packaged]] together into a single [[wp:Chip carrier|package]], containing e.g. [[wp:7400 series|four gates]], and they exist also [[wp:Integrated circuit|chips]] that "implement" a N-input '''OR''', '''AND'''... However these can be done using several gates in their binary "version", so we don't consider them ''elemental''. Indeed considering the [[wp:De Morgan's laws|De Morgan laws]] and other amenities from boolean algebra, we can see that our set of gates is still not really the minimal elemental set of gates. Indeed the discussion about which gates can be considered elemental should not ignore how these gates are created in hardware using "transistors", and the fact that a single purposely chosen gate is all we need to create our circuits. For example, the '''NAND''' gates is a gate similar to the '''AND''', but the output is inverted (''not''ed). All the other gates can be realized using this single gate! So that the minimal set of elemental gates can contain just one element, e.g. the '''NAND''', but the '''NOR''' can be used similarly (see for example [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/nand.html|this link], that shows how a CMOS '''NAND''' and '''AND''' are realized and how they work; observe that the '''NAND''' has 4 transistors while the '''AND''' needs six transistors).
Line 55:
We can easily imagine that a complex digital circuit, if explicitly written in terms of gates '''NOT''', '''OR''' and '''AND''', can become rather hard to be understood and maintained. Exactly how it happens in programming, it is comfortable to build "functional" blocks, containing other (interconnected) functional blocks, containing other functional blocks... until we reach the most elemental blocks that can be "described" only in terms of elemental gates.
More complex "blocks" can be "''
[[wp:Canonical form (Boolean algebra)|analitycal expression(s)]] that then can be [[wp:Karnaugh map|simplified]] and used as model to implement the block using the usable gates. We shall use as [[wp:Boolean logic#Other notations|notation]] a + for ''or'', the product sign · for ''and'' (or nothing: A·B = AB,
<math>\overline{A}B + A\overline{B}</math>, i.e. for the ''xor'' written in terms of ''and'', ''or'' and ''not''.
| |||