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MyHDL - From Python to Silicon!

MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you create a Python model of the hardware system, which you can then simulate, and validate, or export to Verilog or VHDL, and take it to a silicon implementation from there.

On you will find everything you need to get started - and to keep going - with MyHDL. Have fun!

Pages in category "MyHDL"

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