Memory layout of a data structure: Difference between revisions

Content added Content deleted
(omit from Go)
Line 190: Line 190:
[RD:0, RI:1, DSR:1, SG:1, DTR:1, TC:1, TD:1, CD:1, SQD:1, +:1, -:1, SRD:1, RTS:1, SRS:1, STD:1, PG:1, SCD:1, CTS:0, DRS:1, SCS:1, XTC:1, RC:1 ]
[RD:0, RI:1, DSR:1, SG:1, DTR:1, TC:1, TD:1, CD:1, SQD:1, +:1, -:1, SRD:1, RTS:1, SRS:1, STD:1, PG:1, SCD:1, CTS:0, DRS:1, SCS:1, XTC:1, RC:1 ]
</pre>
</pre>
Using Phobos (not tested, possibly wrong):
<lang d>import std.bitmanip;

struct RS232_data {
static if (std.system.endian == std.system.Endian.BigEndian) {
mixin(bitfields!(bool, "carrier_detect", 1,
bool, "received_data", 1,
bool, "transmitted_data", 1,
bool, "data_terminal_ready", 1,
bool, "signal_ground", 1,
bool, "data_set_ready", 1,
bool, "request_to_send", 1,
bool, "clear_to_send", 1,
bool, "ring_indicator", 1,
bool, "", 7));
} else {
mixin(bitfields!(bool, "", 7,
bool, "ring_indicator", 1,
bool, "clear_to_send", 1,
bool, "request_to_send", 1,
bool, "data_set_ready", 1,
bool, "signal_ground", 1,
bool, "data_terminal_ready", 1,
bool, "transmitted_data", 1,
bool, "received_data", 1,
bool, "carrier_detect", 1));
}
}

void main() {
}</lang>


=={{header|Forth}}==
=={{header|Forth}}==