Memory layout of a data structure: Difference between revisions

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m (<lang>)
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=={{header|Ada}}==
=={{header|Ada}}==
<lang ada>
type Bit is mod 2;
type Rs_232_Layout is record
type Bit is mod 2;
⚫
type Rs_232_Layout is record
⚫
Carrier_Detect : Bit;
Received_Data : Bit;
Carrier_Detect : Bit;
Transmitted_Data : Bit;
Received_Data : Bit;
Data_Terminal_ready : Bit;
Transmitted_Data : Bit;
Signal_Ground : Bit;
Data_Terminal_ready : Bit;
Data_Set_Ready : Bit;
Signal_Ground : Bit;
Request_To_Send : Bit;
Data_Set_Ready : Bit;
Clear_To_Send : Bit;
Request_To_Send : Bit;
Ring_Indicator : Bit;
Clear_To_Send : Bit;
⚫
Ring_Indicator : Bit;
end record;
end record;

⚫
for Rs_232_Layout use record
for Rs_232_Layout use record
⚫
Carrier_Detect at 0 range 0..0;
Received_Data at 0 range 1..1;
Carrier_Detect at 0 range 0..0;
Transmitted_Data at 0 range 2..2;
Received_Data at 0 range 1..1;
Data_Terminal_Ready at 0 range 3..3;
Transmitted_Data at 0 range 2..2;
Signal_Ground at 0 range 4..4;
Data_Terminal_Ready at 0 range 3..3;
Data_Set_Ready at 0 range 5..5;
Signal_Ground at 0 range 4..4;
Request_To_Send at 0 range 6..6;
Data_Set_Ready at 0 range 5..5;
Clear_To_Send at 0 range 7..7;
Request_To_Send at 0 range 6..6;
Ring_Indicator at 0 range 8..8;
Clear_To_Send at 0 range 7..7;
⚫
Ring_Indicator at 0 range 8..8;
end record;
end record;
</lang>


=={{header|C}}/{{header|C++}}==
=={{header|C}}/{{header|C++}}==
Note: The order of the fields is implementation-defined (i.e. the first bit might be the least-significant one or the most-significant one). On GCC and MSVC++, the first bit is the least-significant one.
Note: The order of the fields is implementation-defined (i.e. the first bit might be the least-significant one or the most-significant one). On GCC and MSVC++, the first bit is the least-significant one.
<lang c>
struct RS232_data
struct RS232_data
{
{
⚫
unsigned carrier_detect : 1;
unsigned received_data : 1;
unsigned carrier_detect : 1;
unsigned transmitted_data : 1;
unsigned received_data : 1;
unsigned data_terminal_ready : 1;
unsigned transmitted_data : 1;
unsigned signal_ground : 1;
unsigned data_terminal_ready : 1;
unsigned data_set_ready : 1;
unsigned signal_ground : 1;
unsigned request_to_send : 1;
unsigned data_set_ready : 1;
unsigned clear_to_send : 1;
unsigned request_to_send : 1;
unsigned ring_indicator : 1;
unsigned clear_to_send : 1;
⚫
unsigned ring_indicator : 1;
};
};
</lang>
The ":1" gives the number of allocated bits. For unused bits (e.g. pin 11 in the 25-pin version above) the field name can be omitted.
The ":1" gives the number of allocated bits. For unused bits (e.g. pin 11 in the 25-pin version above) the field name can be omitted.


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=={{header|OCaml}}==
=={{header|OCaml}}==


<ocaml>open ExtLib
<lang ocaml>
open ExtLib
class rs232_data = object
class rs232_data = object
val d = BitSet.create 9
val d = BitSet.create 9
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method set_ring_indicator b = (if b then BitSet.set else BitSet.unset) d 8
method set_ring_indicator b = (if b then BitSet.set else BitSet.unset) d 8
end
end
;;
;;</ocaml>
</lang>


=={{header|Perl}}==
=={{header|Perl}}==
<lang perl>
⚫
use Bit::Vector::Minimal qw();
my $vec = Bit::Vector::Minimal->new(size => 24);
use Bit::Vector::Minimal qw();
⚫
my $vec = Bit::Vector::Minimal->new(size => 24);

my %rs232 = reverse (
my %rs232 = reverse (
1 => 'PG Protective ground',
2 => 'TD Transmitted data',
1 => 'PG Protective ground',
3 => 'RD Received data',
2 => 'TD Transmitted data',
4 => 'RTS Request to send',
3 => 'RD Received data',
5 => 'CTS Clear to send',
4 => 'RTS Request to send',
6 => 'DSR Data set ready',
5 => 'CTS Clear to send',
7 => 'SG Signal ground',
6 => 'DSR Data set ready',
8 => 'CD Carrier detect',
7 => 'SG Signal ground',
9 => '+ voltage (testing)',
8 => 'CD Carrier detect',
10 => '- voltage (testing)',
9 => '+ voltage (testing)',
12 => 'SCD Secondary CD',
10 => '- voltage (testing)',
13 => 'SCS Secondary CTS',
12 => 'SCD Secondary CD',
14 => 'STD Secondary TD',
13 => 'SCS Secondary CTS',
15 => 'TC Transmit clock',
14 => 'STD Secondary TD',
16 => 'SRD Secondary RD',
15 => 'TC Transmit clock',
17 => 'RC Receiver clock',
16 => 'SRD Secondary RD',
19 => 'SRS Secondary RTS',
17 => 'RC Receiver clock',
20 => 'DTR Data terminal ready',
19 => 'SRS Secondary RTS',
21 => 'SQD Signal quality detector',
20 => 'DTR Data terminal ready',
22 => 'RI Ring indicator',
21 => 'SQD Signal quality detector',
23 => 'DRS Data rate select',
22 => 'RI Ring indicator',
24 => 'XTC External clock',
23 => 'DRS Data rate select',
24 => 'XTC External clock',
);
);

⚫
$vec->set($rs232{'RD Received data'}, 1);
$vec->get($rs232{'TC Transmit clock'});
$vec->set($rs232{'RD Received data'}, 1);
⚫
$vec->get($rs232{'TC Transmit clock'});
</perl>


=={{header|Python}}==
=={{header|Python}}==
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code below merely defines a dictionary with the pin names corresponding to entries in the dictionary.
code below merely defines a dictionary with the pin names corresponding to entries in the dictionary.


<lang python>
<python># Controlling Fields in a Structure in Python
# Controlling Fields in a Structure in Python


rs232 = {
rs232 = {
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rs232["RD Received data"] = 1
rs232["RD Received data"] = 1
print rs232["TC Transmit clock"]</python>
print rs232["TC Transmit clock"]
</lang>
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