Anonymous user
Memory layout of a data structure: Difference between revisions
Memory layout of a data structure (view source)
Revision as of 05:06, 29 November 2007
, 16 years agono edit summary
m (Switch to header template) |
No edit summary |
||
Line 149:
$vec->set($rs232{'RD Received data'}, 1);
$vec->get($rs232{'TC Transmit clock'});
=={{header|Python}}==
<pre>
# Controlling Fields in a Structure in Python
# This task is easily accomplished with the use of a Python dictionary.
rs232 = {
"PG Protective ground":1,
"TD Transmitted data":2,
"RD Received data":3,
"RTS Request to send":4,
"CTS Clear to send":5,
"DSR Data set ready":6,
"SG Signal ground":7,
"CD Carrier detect":8,
"+ voltage (testing)":9,
"- voltage (testing)":10,
"SCD Secondary CD":12,
"SCS Secondary CTS":13,
"STD Secondary TD":14,
"TC Transmit clock":15,
"SRD Secondary RD":16,
"RC Receiver clock":17,
"SRS Secondary RTS":19,
"DTR Data terminal ready":20,
"SQD Signal quality detector":21,
"RI Ring indicator":22,
"DRS Data rate select":23,
"XTC External clock":24
}
#assignation and retrieval of data is trivial
rs232["RD Received data"] = 1
print rs232["TC Transmit clock"]
</pre>
| |||