Host introspection: Difference between revisions

=={{header|MIPS Assembly}}==

This uses Keith S.'s tutorial at [https://www.chibialiens.com/mips/ Chibialiens.com] to print memory and show register contents.

As I've come to find out, MIPS is a bi-endian architecture (meaning its endianness is implementation-defined rather than a constant trait of the CPU.) In particular, the PlayStation 1 is little-endian, and the Nintendo 64 is big-endian. This can be proven with the test below. (Hardware-specific routines <code>MonitorA0A1RAPC</code> and <code>MemDump</code> are omitted just to keep things brief.)

<lang MIPS> jal Cls ;Zero Graphics cursor position

nop ;on the PlayStation, the instruction AFTER a branch gets executed BEFORE the branch actually occurs.

;The Nintendo 64 didn't have this "feature" but for compatibility's sake

; it's staying in regardless of which version of the code I'm using.

la a2,TestData ;Load address of TestData

lw a0,(a2) ;Load Word into A0 from address in A2

addiu a2,4 ;pointer arithmetic to load the next word.

lw a1,(a2)

move t6,ra

jal MonitorA0A1RAPC

nop

li t6,2 ;Line Count - 2 lines = 16 bytes

jal MemDump ;Dump Ram to screen

nop

halt:

j halt ;loop forever

nop

TestData:

.byte 0xF3,0xF2,0xF1,0xF0 ;this will load as F0F1F2F3 on little-endian machines, and as-is on big-endian

.word 0xF0F1F2F3 ;this will load as F0F1F2F3 regardless of endianness.

</lang>

{{out}}

Register Dump of PlayStation 1:

<pre>a0:F0F1F2F3 a1:F0F1F2F3</pre>

Register Dump of Nintendo 64:

<pre>a0:F3F2F1F0 a1:F0F1F2F3</pre>

It also seems the registers are 32-bit even on the N64. I wouldn't have expected that to be honest...