Generate lower case ASCII alphabet: Difference between revisions
Generate lower case ASCII alphabet in Verilog
(Generate lower case ASCII alphabet in various BASIC dialents (QBasic, True BASIC and Yabasic)) |
(Generate lower case ASCII alphabet in Verilog) |
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Line 2,720:
C:\>cscript /nologo ascii_sequence.vbs A..F
A B C D E F</pre>
=={{header|Verilog}}==
<lang Verilog>module main;
integer i;
initial begin
for(i = 97; i <= 122; i=i+1)
begin
$write("%c ",i);
end
$finish ;
end
endmodule
</lang>
{{out}}
<pre>a b c d e f g h i j k l m n o p q r s t u v w x y z </pre>
=={{header|Vim Script}}==
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