Four bit adder: Difference between revisions

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To interpret and run this code you will need a recent copy of Python, and the MyHDL library from myhdl.org. Both examples integrate test code, and export Verilog and VHDL for hardware synthesis.
To interpret and run this code you will need a recent copy of Python, and the MyHDL library from myhdl.org. Both examples integrate test code, and export Verilog and VHDL for hardware synthesis.


Verbose Code - With integrated Test Demo
Verbose Code - With integrated Test & Demo


<lang python>
<lang python>
#!/usr/bin/env python
#!/usr/bin/env python

""" http://rosettacode.org/wiki/Four_bit_adder
Demonstrate theoretical four bit adder simulation
using And, Or & Invert primitives
⚫
2011-05-10 jc
"""


from myhdl import always_comb, ConcatSignal, delay, intbv, Signal, \
from myhdl import always_comb, ConcatSignal, delay, intbv, Signal, \
Simulation, toVerilog, toVHDL
Simulation, toVerilog, toVHDL
⚫
from random import randrange
from random import randrange



""" define set of primitives
""" define set of primitives
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z.next = a or b
z.next = a or b
return logic
return logic



""" build components using defined primitive set
""" build components using defined primitive set
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fullAdder_2 = fullAdder(c[3],sl[2], c[2],ina(2),inb(2))
fullAdder_2 = fullAdder(c[3],sl[2], c[2],ina(2),inb(2))
fullAdder_3 = fullAdder(co, sl[3], c[3],ina(3),inb(3))
fullAdder_3 = fullAdder(co, sl[3], c[3],ina(3),inb(3))
# create an internal bus for the output list
sc = ConcatSignal(*reversed(sl)) # create internal bus for output list
@always_comb
@always_comb
def logic_list2intbv():
def list2intbv():
sum4.next = sc # assign internal bus to actual output
⚫
sumVar = 0

for i in range(4):
⚫
return halfAdder_0, fullAdder_1, fullAdder_2, fullAdder_3, list2intbv
if sl[i] <> 0:

⚫
sumVar += 2**i
sum4.next = sumVar
⚫
return halfAdder_0,fullAdder_1,fullAdder_2,fullAdder_3, logic_list2intbv


""" define signals and code for testing
""" define signals and code for testing
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t_co, t_s, t_a, t_b, dbug = [Signal(bool(0)) for i in range(5)]
t_co, t_s, t_a, t_b, dbug = [Signal(bool(0)) for i in range(5)]
ina4, inb4, sum4 = [Signal(intbv(0)[4:]) for i in range(3)]
ina4, inb4, sum4 = [Signal(intbv(0)[4:]) for i in range(3)]
sum4 = Signal(intbv(0)[4:])


def test():
def test():
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assert t_co * 16 + sum4 == ina4 + inb4
assert t_co * 16 + sum4 == ina4 + inb4
print
print



""" instantiate components and run test
""" instantiate components and run test
Retrieved from "https://rosettacode.org/wiki/Four_bit_adder"