Four bit adder: Difference between revisions
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(→{{header|C}}: Try to satisfy both the language expression interest and the task requirements.) |
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{{task}} |
{{task}} |
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The aim of this task is to "''simulate''" a four |
The aim of this task is to "''simulate''" a four-bit adder "chip". This "chip" can be realized using four [[wp:Adder_(electronics)#Full_adder|1-bit full adder]]s. Each of these 1-bit full adders can be with two [[wp:Adder_(electronics)#Half_adder|half adder]]s and an ''or'' [[wp:Logic gate|gate]]. Finally a half adder can be made using a ''xor'' gate and an ''and'' gate. The ''xor'' gate can be made using two ''not''s, two ''and''s and one ''or''. |
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| ⚫ | '''Not''', '''or''' and '''and''', the only allowed "gates" for the task, can be "imitated" by using the [[Bitwise operations|bitwise operators]] of your language. If there is not a ''bit type'' in your language, to be sure that the ''not'' does not "invert" all the other bits of the basic type (e.g. a byte) we are not interested in, you can use an extra ''nand'' (''and'' then ''not'') with the constant 1 on one input. |
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'''Not''', '''or''' and '''and''', the only allowed "gates" for the task, can |
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| ⚫ | |||
Instead of optimizing and reducing the number of |
Instead of optimizing and reducing the number of gates used for the final 4-bit adder, build it in the most straightforward way, ''connecting'' the other "constructive blocks", in turn made of "simpler" and "smaller" ones. |
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Schematics of these "constructive blocks" are |
Schematics of these "constructive blocks" are given here. |
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[[File:xor.png|thumb|Xor gate done with ands, ors and nots]] |
[[File:xor.png|thumb|Xor gate done with ands, ors and nots]] |
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[[File:halfadder.png|thumb|A half adder]] |
[[File:halfadder.png|thumb|A half adder]] |
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[[File:fulladder.png|thumb|A full adder]] |
[[File:fulladder.png|thumb|A full adder]] |
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[[File:4bitsadder.png|thumb|A 4- |
[[File:4bitsadder.png|thumb|A 4-bit adder]] |
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Solutions should try to be as descriptive as possible, making as easy as possible to identify "connections" between higher-order "blocks". It is not mandatory to replicate the syntax of higher-order blocks in the atomic "gate" blocks, i.e. basic "gate" operations can be performed as usual bitwise operations, or they can be "wrapped" in a ''block'' in order to expose the same syntax of higher-order blocks, at implementers' choice. |
Solutions should try to be as descriptive as possible, making it as easy as possible to identify "connections" between higher-order "blocks". It is not mandatory to replicate the syntax of higher-order blocks in the atomic "gate" blocks, i.e. basic "gate" operations can be performed as usual bitwise operations, or they can be "wrapped" in a ''block'' in order to expose the same syntax of higher-order blocks, at implementers' choice. |
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To test the implementation, show the sum of two four- |
To test the implementation, show the sum of two four-bit numbers (in binary). |
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=={{header|C}}== |
=={{header|C}}== |
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#define NOT(X) (~(X)&1) |
#define NOT(X) (~(X)&1) |
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/* a shortcut to "implement" a XOR using only NOT, AND and OR gates |
/* a shortcut to "implement" a XOR using only NOT, AND and OR gates, as |
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task requirements constrain */ |
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C has '^' as a bitwise-XOR, but that doesn't follow the task's |
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building-block approach. */ |
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#define XOR(X,Y) ((NOT(X)&(Y)) | ((X)&NOT(Y))) |
#define XOR(X,Y) ((NOT(X)&(Y)) | ((X)&NOT(Y))) |
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/* The above define is functionally equivalent to |
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#define XOR(X,Y) (X^Y) */ |
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void halfadder(IN a, IN b, OUT s, OUT c) |
void halfadder(IN a, IN b, OUT s, OUT c) |
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