Four bit adder: Difference between revisions
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The aim of this task is to "''simulate''" a four bits adder "chip". This "chip" can be realized using four [[wp:Adder_(electronics)#Full_adder|1 bit full adder]]s. Each of these 1 bit full adders can be realized using two [[wp:Adder_(electronics)#Half_adder|half adder]]s and an ''or'' [[wp:Logic gate|gate]]. And finally a half adder can be made using a ''xor'' gate and an ''and'' gate. The ''xor'' gate can be realized using two ''not''s, two ''and''s and one ''or''. |
The aim of this task is to "''simulate''" a four bits adder "chip". This "chip" can be realized using four [[wp:Adder_(electronics)#Full_adder|1 bit full adder]]s. Each of these 1 bit full adders can be realized using two [[wp:Adder_(electronics)#Half_adder|half adder]]s and an ''or'' [[wp:Logic gate|gate]]. And finally a half adder can be made using a ''xor'' gate and an ''and'' gate. The ''xor'' gate can be realized using two ''not''s, two ''and''s and one ''or''. |
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Instead of optimizing and reducing the number of used gates for the final 4-bits-adder, build it in the most straightforward way, ''connecting'' the other "constructive blocks", in turn made of "simpler" and "smaller" one. |
Instead of optimizing and reducing the number of used gates for the final 4-bits-adder, build it in the most straightforward way, ''connecting'' the other "constructive blocks", in turn made of "simpler" and "smaller" one. |
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Schematics of these "constructive blocks" are here given |
Schematics of these "constructive blocks" are here given. |
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[[File:xor.png|thumb|Xor gate done with ands, ors and nots]] |
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[[File:halfadder.png|thumb|A half adder]] |
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[[File:fulladder.png|thumb|A full adder]] |
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[[File:4bitsadder.png|thumb|A 4-bits-adder]] |
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Solutions should try to be as descriptive as possible, making as easy as possible to identify "connections" between higher-order "blocks". It is not mandatory to replicate the syntax of higher-order blocks in the atomic "gate" blocks, i.e. basic "gate" operations can be performed as usual bitwise operations, or they can be "wrapped" in a ''block'' in order to expose the same syntax of higher-order blocks, at implementers' choice. |
Solutions should try to be as descriptive as possible, making as easy as possible to identify "connections" between higher-order "blocks". It is not mandatory to replicate the syntax of higher-order blocks in the atomic "gate" blocks, i.e. basic "gate" operations can be performed as usual bitwise operations, or they can be "wrapped" in a ''block'' in order to expose the same syntax of higher-order blocks, at implementers' choice. |
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