Flow-control structures: Difference between revisions

* An additional <code>BSR</code> can be used for nearby subroutines. This takesis fewer bytes to encodequicker than a <code>JSR</code> but has a limited range. It is also <i>not</i> relocatable, in the sense that if you copy a routine to RAM that uses this instruction and try to execute it there, unless you also copied the routine that you're <code>BSR</code>ing to, you're in for a nasty surprise. Many assemblers will auto-convert JSR to BSR and there's no easy way to conditionally stop that from happening except by inlining bytecode.

* <code>DBRA</code> is used for looping. A register operand is decremented with each loop. The loop terminates when the value in the register underflows from <tt>0</tt> to FFFF<tt>0xFFFF</tt>. As a result, the number of times you want to loop must be reduced by one. <code>DBRA</code> stands for "decrement, branch always" and there are other condition codes you can use, that will decrement the register operand (at word length) and branch <i>unless</i> the condition is met.

* <code>TRAP #</code> is often used for error handling. These can occur automatically (such as if a nonexistent machine instruction is executed or the CPU attempts to divide by zero), or at the programmer's request (such as <code>TRAPV</code> to detect signed overflow or just TRAP # to execute a specific trap.) Traps can also be used by the firmware to perform built-in tasks such as reading a keyboard or mouse input. Some systems (such as the Sega Genesis and NEO GEO) allow the programmer to alter the destination of the traps, allowing for custom error handlers. (However, these locations are usually in ROM and thus cannot be changed at runtime.)