Empty program: Difference between revisions
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(Empty program en Asymptote) |
(Empty program en Verilog) |
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An empty file is the smallest valid script, but running it does nothing.
<lang verbexx></lang>
=={{header|Verilog}}==
<lang Verilog>module main;
endmodule</lang>
=={{header|VHDL}}==
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