Conditional structures: Difference between revisions
Conditional structures en Verilog
(Conditional structures en Verilog) |
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Line 7,315:
n = 1 @CASE results: n == 1(2c)
n = 2 @CASE results: else</lang>
=={{header|Verilog}}==
===if-else===
<lang Verilog>
if( expr_booleana ) command1;
else command2;
</lang>
===case===
<lang Verilog>
case( expr_booleana )
valor1: command1;
valor2: command2;
...
default: commandN;
endcase
</lang>
=={{header|Visual Basic}}==
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