Category:SystemVerilog: Difference between revisions
Content added Content deleted
No edit summary |
(Use Template:Language for great effect. :)) |
||
| Line 1: | Line 1: | ||
SystemVerilog is a language used for hardware design and verification. It is defined by IEEE standard 1800-2005, which extends the hardware description language Verilog (IEEE 1364-2001). SystemVerilog has strong support for concurrency, but though the execution model is based on a single thread that provides the illusion of concurrency via a simulation model known as two-list simulation: first all the "outputs" (of all processes) are calculated as functions of the current inputs; and then the inputs to all processes are updated from the outputs that drive them. So, for example: |
{{language|SystemVerilog}} is a language used for hardware design and verification. It is defined by IEEE standard 1800-2005, which extends the hardware description language Verilog (IEEE 1364-2001). SystemVerilog has strong support for concurrency, but though the execution model is based on a single thread that provides the illusion of concurrency via a simulation model known as two-list simulation: first all the "outputs" (of all processes) are calculated as functions of the current inputs; and then the inputs to all processes are updated from the outputs that drive them. So, for example: |
||
<lang:SystemVerilog> |
<lang:SystemVerilog> |
||
| Line 22: | Line 22: | ||
* (temporal) assertions |
* (temporal) assertions |
||
* random sequence generation, and constrained random variables |
* random sequence generation, and constrained random variables |
||
---- |
|||
Many [[Reports:Tasks not implemented in SystemVerilog|tasks]] are not yet implemented. |
|||