Category:MIPS Assembly: Difference between revisions
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Puppydrum64 (talk | contribs) (→Instruction Set: having this info is kind of redundant since the user can just look at the documentation.) |
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==Instruction Set== |
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===ADDU=== |
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* Stands for: '''A'''dd '''U'''nsigned |
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* Usage: <code>addu $dest,$operand1,$operand2</code> |
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* Example: <code>addu $t2,$t1,$t0</code> |
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* Effect: Adds the contents of <code>$t1</code> to <code>$t0</code> and stores the result in <code>$t2</code>. |
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* Notes: This will ''not'' cause an overflow exception if the operands were each less than <tt>0x7FFFFFFF</tt> and the result is greater than that. |
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===ADDIU=== |
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* Stands for: '''A'''dd '''I'''mmediate '''U'''nsigned |
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* Usage: <code>addiu $dest,$operand1,constant</code> |
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* Example: <code>addiu $t0,$t0,0x1234</code> |
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* Effect: Adds <tt>0x1234</tt> to <code>$t0</code> and stores the result in <code>$t0</code>. |
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* Notes: This will ''not'' cause an overflow exception if the register operand is less than <tt>0x7FFFFFFF</tt> and the result is greater. The constant value is sign-extended if it is less than 32-bit. If the destination and the register operand are the same register, you can omit one of them like so: <code>addiu $t0,0x1234</code> |
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The related pseudo-instruction <code>subiu</code> is an alternative if you wish to express the idea that you're subtracting an unsigned number. It gets converted to <code>addiu</code> and the constant operand is replaced with its two's complement. In other words, <code>subiu $t0,1</code> is the same as <code>addiu $t0,-1</code>. |
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===BEQ=== |
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* Stands for: '''B'''ranch if '''Eq'''ual |
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* Usage: <code>beq $operand1,$operand2,label</code> |
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* Example: <code>beq $t0,$t1,T0_equals_T1</code> |
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* Effect: Compares the register operands, and if they're equal, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>beq</code>. This is not a typo, that's how MIPS works. |
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===BEQZ=== |
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* Stands for: '''B'''ranch if '''Eq'''ual to '''Z'''ero |
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* Usage: <code>beqz $operand1,label</code> |
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* Example: <code>beqz $t0,T0_is_Zero</code> |
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* Effect: If the register operand contains 0, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>beqz</code>. This is not a typo, that's how MIPS works. |
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===BNE=== |
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* Stands for: '''B'''ranch if '''N'''ot '''E'''qual |
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* Usage: <code>bne $operand1,$operand2,label</code> |
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* Example: <code>bne $t0,$t1,T0_Not_Equal_to_T1</code> |
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* Effect: Compares the register operands, and if they're not equal, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>bne</code>. This is not a typo, that's how MIPS works. |
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===BNEZ=== |
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* Stands for: '''B'''ranch if '''N'''ot '''E'''qual to '''Z'''ero |
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* Usage: <code>bnez $operand1,label</code> |
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* Example: <code>bnez $t0,T0_Nonzero</code> |
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* Effect: If the register operand doesn't contain zero, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>bnez</code>. This is not a typo, that's how MIPS works. |
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==See Also== |
==See Also== |