Category:MIPS Assembly: Difference between revisions
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MIPS has a whopping 32 registers. Most of them are technically general purpose but calling conventions dictate what each should be used for. Unlike most assembly languages, where you have to remember what the calling conventions are, MIPS assemblers typically give the registers abbreviated names that imply how to use them. For example, <code>$v0</code> and <code>$v1</code> are the return values of functions, and <code>$a0</code> through <code>$a3</code> are function arguments. While a frame pointer does exist, having four registers dedicated to passing function arguments means you won't have to twiddle around with stack frames nearly as much as you would on other CPUs. |
MIPS has a whopping 32 registers. Most of them are technically general purpose but calling conventions dictate what each should be used for. Unlike most assembly languages, where you have to remember what the calling conventions are, MIPS assemblers typically give the registers abbreviated names that imply how to use them. For example, <code>$v0</code> and <code>$v1</code> are the return values of functions, and <code>$a0</code> through <code>$a3</code> are function arguments. While a frame pointer does exist, having four registers dedicated to passing function arguments means you won't have to twiddle around with stack frames nearly as much as you would on other CPUs. |
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==RISC CPU== |
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MIPS is a <b>R</b>educed '''I'''nstruction '''S'''et '''C'''omputer architecture, which means that it has fewer instructions than an architecture like [[x86 Assembly]], in exchange for more registers and quicker overall processing. As with most RISC CPUs, all instructions are the same size, in this case, 32 bit. Unfortunately, this poses a problem: How do you encode an instruction like <code>li $t0,0x12345678</code> into 32 bits, where the instruction itself has a 32-bit operand? Well, you can't. Like ARM, there are some numbers that are too big for MIPS to load in a single instruction. |
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<lang mips>li t0,0xFFFFFFFF ;this won't compile as the operand is too large.</lang> |
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Instead you'll have to do a little trickery: |
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<lang mips>li t0, 0 |
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subiu t0,1</lang> |
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==Pseudo-instructions== |
==Pseudo-instructions== |
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