Category:MIPS Assembly: Difference between revisions

← Older edit

Category:MIPS Assembly (view source)

Revision as of 18:56, 9 July 2022

2,897 bytes removed , 1 year ago

m

→‎See Also

Puppydrum64

1,489

edits

Revision as of 18:33, 9 July 2022 (view source) Puppydrum64 (talk \| contribs) m (→‎BNE) ← Older edit		Latest revision as of 18:56, 9 July 2022 (view source) Puppydrum64 (talk \| contribs) m (→‎See Also)
(6 intermediate revisions by the same user not shown)
Line 40: Branch delay slots affect all versions of MIPS. This is the phenomenon where the instruction immediately after a branch is actually executed <i>before</i> the branch takes place. <lang mips>jal PrintString addiu $a0,1 ;~~this~~once ~~instruction~~the isprogram ~~executed~~counter ~~BEFORE~~becomes the ~~call~~address toof PrintString, this instruction has already isfinished.</lang> On a "normal" CPU with no pipeline, the instruction after a call is not executed whatsoever until after it returns. This would have the same outcome as the following, except the above version is faster than this one: Line 53 ⟶ 54: nop</lang> Most assemblers will refuse to allow your code to compile if certain instructions are in the branch delay slot. A branch delay slot cannot contain a branch. ~~==Instruction Set==~~ <lang mips>bne $t0,$t1,skip ~~===ADDU===~~ jal DoThing ;this can't be in a branch delay slot, and therefore won't compile. * Stands for: '''A'''dd '''U'''nsigned skip:</lang> * Usage: <code>addu $dest,$operand1,$operand2</code> * Example: <code>addu $t2,$t1,$t0</code> * Effect: Adds the contents of <code>$t1</code> to <code>$t0</code> and stores the result in <code>$t2</code>. * Notes: This will ''not'' cause an overflow exception if the operands were each less than <tt>0x7FFFFFFF</tt> and the result is greater than that. Placing a <tt>nop</tt> in the slot instead will fix this. ~~===ADDIU===~~ <lang mips>bne $t0,$t1,skip * Stands for: '''A'''dd '''I'''mmediate '''U'''nsigned nop ;branch delay slot * Usage: <code>addiu $dest,$operand1,constant</code> jal DoThing * Example: <code>addiu $t0,$t0,0x1234</code> skip:</lang> * Effect: Adds <tt>0x1234</tt> to <code>$t0</code> and stores the result in <code>$t0</code>. * Notes: This will ''not'' cause an overflow exception if the register operand is less than <tt>0x7FFFFFFF</tt> and the result is greater. The constant value is sign-extended if it is less than 32-bit. If the destination and the register operand are the same register, you can omit one of them like so: <code>addiu $t0,0x1234</code> ~~===BNE===~~ * Stands for: '''B'''ranch if '''N'''ot '''E'''qual * Usage: <code>bne $operand1,$operand2,label</code> * Example: <code>bne $t0,$t1,T0NotEqualtoT1</code> * Effect: Compares the register operands, and if they're not equal, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>bne</code>. This is not a typo, that's how MIPS works. ~~===BEQ===~~ * Stands for: '''B'''ranch if '''Eq'''ual * Usage: <code>beq $operand1,$operand2,label</code> * Example: <code>beq $t0,$t1,T0NotEqualtoT1</code> * Effect: Compares the register operands, and if they're equal, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>beq</code>. This is not a typo, that's how MIPS works. ~~===BEQZ===~~ * Stands for: '''B'''ranch if '''Eq'''ual to '''Z'''ero * Usage: <code>beqz $operand1,label</code> * Example: <code>beqz $t0,T0_is_Zero</code> * Effect: If the register operand contains 0, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>beqz</code>. This is not a typo, that's how MIPS works. ~~===BNE===~~ * Stands for: '''B'''ranch if '''N'''ot '''E'''qual * Usage: <code>bne $operand1,$operand2,label</code> * Example: <code>bne $t0,$t1,T0_Not_Equal_to_T1</code> * Effect: Compares the register operands, and if they're not equal, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>bne</code>. This is not a typo, that's how MIPS works. ~~===BNEZ===~~ * Stands for: '''B'''ranch if '''N'''ot '''E'''qual to '''Z'''ero * Usage: <code>bnez $operand1,label</code> * Example: <code>bnez $t0,T0_Nonzero</code> * Effect: If the register operand doesn't contain zero, adds (signed) the specified offset to <code>PC</code>. (usually a labeled line of code that the assembler translates to a calculated offset.) Otherwise, execution falls through to the ''instruction after the instruction after'' the <code>bnez</code>. This is not a typo, that's how MIPS works. ==See Also== * [[wp:MIPS_architecture\|MIPS architecture]] * [https://en.m.wikibooks.org/wiki/N64_Programming/CPU_overview Overview of N64 Architecture] * [https://www.chibialiens.com/mips/ A multiplatform tutorial of MIPS Assembly programming with examples and downloadable dev tools]