Category:MIPS Assembly: Difference between revisions
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<lang mips>li t0, 0
subiu t0,1</lang>
==Pseudo-instructions==▼
MIPS has a form of "hardware macros" that help out with tasks that it can't do alone. It has a special register that exists solely for the execution of these macros, which is not usable by the programmer directly. Assemblers will generally let you use these "pseudo-instructions" as if they were real instructions, even if they technically don't exist. Knowing what instructions are "real" and which ones aren't usually doesn't matter much, since you won't be doing self-modifying code on the MIPS anyway (for reasons we'll get into later)▼
==Alignment==
Unlike other RISC CPUs, MIPS actually <i>can</i> load data from unaligned memory without faulting. However, it can't use the normal <code>LW</code> and <code>SW</code> commands in order to do so. It should be noted that this only applies to data; instructions do need to be 32-bit aligned at all times. Most assemblers have an <code>.align</code> directive that can do the job easily.
▲==Pseudo-instructions==
▲MIPS has a form of "hardware macros" that help out with tasks that it can't do alone. It has a special register that exists solely for the execution of these macros, which is not usable by the programmer directly. Assemblers will generally let you use these "pseudo-instructions" as if they were real instructions, even if they technically don't exist. Knowing what instructions are "real" and which ones aren't usually doesn't matter much, since you won't be doing self-modifying code on the MIPS anyway (for reasons we'll get into later)
==Bi-Endian==
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Branch delay slots affect all versions of MIPS. This is the phenomenon where the instruction immediately after a branch is actually executed <i>before</i> the branch takes place.
<lang mips>jal PrintString
addiu $a0,1 ;
On a "normal" CPU with no pipeline, the instruction after a call is not executed whatsoever until after it returns.
This would have the same outcome as the following, except the above version is faster than this one:
Line 52 ⟶ 53:
jal bar
nop</lang>
Most assemblers will refuse to allow your code to compile if certain instructions are in the branch delay slot. A branch delay slot cannot contain a branch.
<lang mips>bne $t0,$t1,skip
jal DoThing ;this can't be in a branch delay slot, and therefore won't compile.
skip:</lang>
Placing a <tt>nop</tt> in the slot instead will fix this.
<lang mips>bne $t0,$t1,skip
nop ;branch delay slot
jal DoThing
skip:</lang>
==See Also==
* [[wp:MIPS_architecture|MIPS architecture]]
* [https://en.m.wikibooks.org/wiki/N64_Programming/CPU_overview Overview of N64 Architecture]
* [https://www.chibialiens.com/mips/ A multiplatform tutorial of MIPS Assembly programming with examples and downloadable dev tools]
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