Category:MyHDL: Difference between revisions
Content added Content deleted
(Created page with "{{stub}}{{language}}") |
No edit summary |
||
(One intermediate revision by the same user not shown) | |||
Line 1: | Line 1: | ||
MyHDL - From Python to Silicon! |
|||
{{stub}}{{language}} |
|||
MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you create a Python model of the hardware system, which you can then simulate, and validate, or export to Verilog or VHDL, and take it to a silicon implementation from there. |
|||
On www.myhdl.org you will find everything you need to get started - and to keep going - with MyHDL. Have fun! |
Latest revision as of 09:51, 9 May 2011
MyHDL - From Python to Silicon!
MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you create a Python model of the hardware system, which you can then simulate, and validate, or export to Verilog or VHDL, and take it to a silicon implementation from there.
On www.myhdl.org you will find everything you need to get started - and to keep going - with MyHDL. Have fun!